Find what changed. Understand what it affects. Focus your engineering review. Fixed-scope consulting engagements that produce prioritized review targets, source-linked explanations and explicit unresolved gaps.
Fixed scope. Three business day standard evaluation. No ranked review packet produced → no fee. Review concentration does not guarantee a reduction in total engineering effort; measured customer outcomes are not yet established. Reducing a review queue does not establish correctness or clearance outside it. The Evaluation Gate preserves claim boundaries; it cannot approve signoff, fabrication, tapeout, benchmark validity, or production readiness.
Review concentration across supported RTL and PCB inputs, with source-linked dependency explanations, assumption-conflict detection and unresolved gaps. The compiler-hardware lane remains a separate early capability.
Compresses RTL review surfaces before formal verification, DV, or manual review begins. It ranks supported signal changes, limited local cones, FSM drift, and candidate assertion questions for engineer inspection. Complete automatic evidence-dependency extraction is unfinished.
Compresses board, BOM, fab-package, and firmware-to-board assumptions into ranked review blockers. Declared dependency paths explain which supplied evidence needs another look; unresolved external evidence stays explicit. Gate means claim/action boundary, not manufacturing approval.
Fixture-backed v0.1 lane for compiler output, ISA assumptions, simulator behavior, runtime assumptions, benchmark claims, and RTL evidence. Early lane means normalized evidence packet, not compiler verification.
Reducing a review queue does not establish correctness or clearance outside it. Ark Axiom blocks correctness, signoff, manufacturing, benchmark, and replacement claims. The packet supports review concentration; total engineering effort savings require measured customer outcomes.
packet_authorizes_execution:falsehuman_operator_handoff:trueBefore Ark Axiom reviews RTL, PCB, BOM, firmware, fab-package, or compiler-hardware evidence, the evaluation scope is converted into a bounded authority envelope.
Axiom Evaluation Gate controls what a review agent may read, derive, claim, export, and hand off during a bounded hardware evaluation. The gate defines what artifacts may be inspected, what evidence may be derived, what claims are blocked, what outputs may be exported, what must be handed to a human engineer, and what remains outside scope.
The review agent may rank, localize, summarize, and preserve evidence. It may not approve signoff, fabrication, tapeout, benchmark validity, compiler correctness, RTL correctness, BOM correctness, DRC/ERC, SI/PI, safety, or production readiness.
{
"axiom_evaluation_gate": {
"gate_id": "AXIOM_EVAL_GATE_v0_1",
"review_mode": "rtl_review | pcb_eco | fab_readiness | firmware_hardware | compiler_hardware",
"scope_envelope": {
"artifact_types_allowed": ["rtl", "pcb", "bom", "firmware_config", "compiler_evidence"],
"source_access": "sanitized | nda | public_fixture",
"production_access_allowed": false,
"credential_access_allowed": false,
"external_side_effect_allowed": false
},
"allowed_agent_actions": [
"rank_review_targets",
"localize_evidence",
"summarize_drift",
"emit_reason_codes",
"hash_artifacts",
"produce_review_packet"
],
"blocked_agent_actions": [
"approve_signoff",
"approve_fabrication",
"approve_tapeout",
"approve_benchmark",
"modify_source_artifacts",
"submit_to_fab",
"replace_engineer_review"
],
"human_operator_handoff": true,
"packet_authorizes_execution": false,
"zero_signoff_authority": true
}
}
These boundaries are not disclaimers. They are the architecture. A review agent that overclaims is a liability, not a tool.
Synthetic conflict examples, controlled ECOs and historical replay cases on public boards and public RTL. These are not measured customer outcomes. Customer artifacts evaluated only under NDA. View the packet mode map → · Open evidence graph →
The declared graph links prior USB bring-up evidence to both USB_D_P routing and the supplied usb_dp firmware assignment. Changes to those dependencies mark that evidence for review.
These arrows record declared dependencies, not a complete causal proof. No external USB test log is supplied; external evidence dependencies remain incomplete. The result identifies conflicts in the supplied model, not an electrical failure or comprehensive design clearance.
Implemented capabilities apply within supported inputs and declared assumptions. A smaller review queue does not establish correctness or clearance outside it.
| Capability | RTL | PCB |
|---|---|---|
| Revision localization | Implemented within supported constructs | Implemented within supported inputs |
| Review prioritization | Implemented | Implemented |
| Dependency explanations | Limited local-cone analysis | Integrated declared dependency paths |
| Constraint conflicts | Not a general RTL correctness checker | Board/BOM/assembly/firmware checks |
| Evidence applicability | Partial; complete automatic extraction unfinished | Declared dependency impact; external evidence unresolved |
| Comprehensive design clearance | Not established | Not established |
Historical replay, current regression testing, abstract Lean policy checks and customer-effectiveness evidence answer different questions. The published RTL replay results belong to the original engine version and have not been requalified after the recent comparator fixes.
| Evidence Track | Evidence & Status | What It Supports | What It Does Not Claim |
|---|---|---|---|
| Historical RTL Replay | 15 / 15 overlap cases · original-version replay | Historical ranked-target overlap with public repair contexts, including the Ibex 2,278-lines-to-one-target result | Independent bug discovery, current-version effectiveness, effort saved, formal proof, RTL correctness, DV signoff |
| Current Regression Testing | 11 RTL + 37 math/PCB tests passed · 11 Oct 2026 | Regression coverage for comparator failure handling and supported model, dependency and conflict behavior | Customer effectiveness, complete extraction, replay requalification, comprehensive RTL or PCB correctness |
| Abstract Lean Policy Checks | Policy compiled · supplied abstract model | Abstract policy properties about declared dependencies and review decisions | Correctness of the parser, Python implementation, extracted dependency graph or customer hardware |
| Customer-Effectiveness Evidence | Not yet established | Future measured engagements can assess useful review concentration and total engineering effort | Guaranteed engineering time savings, customer ROI, production design clearance |
| Synthetic PCB Conflict Example | 3 modeled conflicts · declared USB evidence paths | Board/BOM value, assembly population and supplied firmware-pad conflicts; prior USB bring-up evidence marked for review | A customer result, electrical failure proof, automatic firmware extraction or validated external bring-up evidence |
| RTL Assertion Gate | 5 cases · 2 strong · 3 partial | Candidate SVA, assumptions, vacuity warnings, human approval questions | Final specs, proof success, non-vacuous proof, DV engineering replacement |
| Forward-Progress Review Gate v0.1 | 12 synthetic fixtures · deterministic packets | Property, assumption, fairness, wait-dependency, vacuity, and counterexample-review evidence inventory; formal engine not used | Formal proof, RTL correctness, deadlock freedom, starvation freedom, formal closure, tapeout approval |
| Forward-Progress Formal Harness v0.2 | 7 synthetic fixtures · 3 proofs · 3 counterexamples · 1 vacuity case | Yosys + SymbiYosys + Z3 bounded formal evidence with raw artifacts, deterministic Ark packets, and bounded-vs-unbounded scope recorded | Production RTL effectiveness, unbounded liveness proof, protocol completeness, commercial-tool support, formal closure, RTL correctness |
| PCB ECO Gate | System76 Launch public KiCad history | Board-revision review blockers for routing, power, ground, debug, boot/control | DRC/ERC, SI/PI, thermal validation, manufacturing readiness |
| PCB Evidence Graph Consistency Gate v0.1 | 12 synthetic fixtures · 13 packets · deterministic replay | Cross-artifact review across PCB source, BOM, assembly context, and firmware pin configuration; the extra packet records the same board/BOM under a second context profile | Electrical validation, DRC/ERC, DFM approval, fabrication readiness, firmware correctness, manufacturing signoff, release authorization |
| BOM / AVL-Style Evidence | nSealr TROPIC01 public BOM path | BOM/AVL-style review evidence in controlled and real before/after BOM path | BOM correctness, AVL approval, substitute-part suitability, DFM |
| PCB Fab Readiness Gate | Complete + missing fixture packages | Checks for expected source, Gerber, drill, BOM, CPL/PNP, stackup, DRC/ERC presence | File correctness, manufacturability, electrical behavior, certification |
| Firmware-Hardware Gate | 7 deterministic fixtures | Review blockers for MCU identity, pin assumptions, UART/I2C/SPI drift, boot conflicts | Firmware correctness, HIL testing, board bring-up, safety certification |
| Compiler-Hardware Assumption Gate v0.1 | Fixture-backed packet · 16 targets · SHA-256 verified | Assumption review across ISA, simulator, runtime, benchmark, memory, and RTL evidence | Compiler correctness, simulator/RTL equivalence, benchmark validation, performance portability, hardware readiness |
A fixed-scope engagement, not a software deployment. Runs alongside your existing review workflows without replacing EDA, DRC/ERC, or signoff.
Hardware teams that need review compression before signoff — not autonomous AI making engineering decisions.
One bounded RTL, PCB/BOM, fab-readiness, firmware-hardware, or early compiler-hardware assumption review packet. Scope and NDA agreed before intake.